Board Design Tips - 2021.1 English

Versal ACAP Board System Design Methodology Guide (UG1506)

Document ID
UG1506
Release Date
2021-08-04
Version
2021.1 English

When designing a board, it is important to consider which interfaces and pins will assist with debug capability beyond configuration. For example, Xilinx recommends that you ensure the JTAG interface is accessible even when the interface is not the primary configuration mode. The JTAG interface allows you to check the device ID and device DNA information, and you can use the interface to enable indirect flash programming solutions during prototyping.

In addition, signals such as DONE are critical for device configuration debug. Xilinx recommends that you connect the DONE signals to light-emitting diodes (LEDs) using LED drivers and pull-ups.

For recommended pull-up values, see this link in the Versal ACAP PCB Design User Guide (UG863) and Versal ACAP Schematic Review Checklist (XTP546).