Interface Bandwidth Validation - 2021.1 English

Versal ACAP Board System Design Methodology Guide (UG1506)

Document ID
UG1506
Release Date
2021-08-04
Version
2021.1 English

Create small connectivity designs to validate each interface on the device. These small designs exercise only the specific hardware interface, which enables the following:

  • Full DRC checks on pinout, clocking, and timing
  • Hardware test design when the board is returned
  • Rapid implementation through the Vivado tools, providing the fastest way to debug the interface

There are multiple options to assist in generating test data for these interfaces. For some of the interface IP cores, the Vivado tools can provide the test designs:

  • IBERT for SerDes
  • Example design within IP cores
Tip: If a test design does not exist, consider using AXI traffic generators.

You might need to create a separate design for a system-level test in a production environment. Usually, this is a single design that includes tested interfaces and optionally includes processors. You can construct this design using the small connectivity designs to take advantage of design reuse. Although this design is not required early in the flow, it can enable better DRC checks and early software development, and you can quickly create it using the Vivado IP integrator.