Additional I/O pin planning steps are required when using Xilinx Memory IP and Advanced IO Wizard IP. After the IP is customized, assign the top-level IP ports to physical package pins in either the elaborated or synthesized design in the Vivado IDE. All of the ports associated with each Memory IP or Advanced IO Wizard IP are grouped together into an I/O Port Interface for easier identification and assignment. The Advanced I/O Planner is provided to assist you with assigning I/O pin groups to XPHY NIBBLESLICEs on the physical device pins. For more information, see this link in the Versal ACAP SelectIO Resources Architecture Manual (AM010), this link in the Advanced I/O Wizard LogiCORE IP Product Guide (PG320), or the appropriate product guide for your memory IP.
Important: PCB Guidelines for Memory Interfaces in Versal ACAP PCB Design User Guide (UG863) contains design and pinout guidelines. Follow the trace length match recommendations in this guide, verify that the correct termination is used, and validate the pinout by running the DRCs after I/O assignment in the Advanced I/O Planner.