Netlist-Based I/O Planning - 2021.1 English

Versal ACAP Board System Design Methodology Guide (UG1506)

Document ID
UG1506
Release Date
2021-08-04
Version
2021.1 English

Xilinx recommends assigning I/Os and clock logic constraints after the design has been synthesized. For Versal devices, Xilinx recommends instantiating all IP and I/Os along with basic logic in an RTL project. The project can then be synthesized. For Xilinx IP, such as memory interfaces and high-speed I/O interfaces, the Advanced IO Wizard allows for correct-by-construction pinout assignment. For legacy, low-performance interfaces using I/O logic, pinout can be performed using drag-and-drop onto the Package window.