NoC and DDRMC Power Estimation - 2021.1 English

Versal ACAP Board System Design Methodology Guide (UG1506)

Document ID
UG1506
Release Date
2021-08-04
Version
2021.1 English

The Versal ACAP XPE has a dedicated sheet for the NoC and DDR4 memory controller (DDRMC) power estimation, as shown in the following figure.

Figure 1. XPE NoC-DDRMC Power Sheet
Following are the recommended flows to enable accurate power estimation:
Manual Entry Flow
Use this flow for early power estimation when a Vivado tools design is not yet available or ready.
  1. Manually specify the configuration of the NoC data path to get the estimated power.
  2. Create a DDR interface using the DDRMC Wizard if you are using a hard DDR in your design.
Vivado Tools Export/Import Flow
After an IP integrator design is available in the Vivado tools with NoC present as an IP, use this flow for a more accurate NoC power estimation. In this flow, the Vivado tools generate the .xpe file with all the information required for NoC power estimation.
  1. In the Vivado IP integrator design when validate_bd_design is run, the NOC_Power.xpe file is generated with all the NoC configurations.
  2. After the .xpe file for the NoC design is generated, import this .xpe file into the Versal ACAP XPE NoC_DDRMC sheet.
  3. XPE uses NoC and DDRMC data from the .xpe file based on the NoC solution from the IP integrator block design.
Note: For more information, see the Xilinx Power Estimator User Guide for Versal ACAP (UG1275).