Pre-RTL I/O Planning - 2021.1 English

Versal ACAP Board System Design Methodology Guide (UG1506)

Document ID
UG1506
Release Date
2021-08-04
Version
2021.1 English

Pre-RTL I/O planning is not recommended for Versal devices due to the heavy dependency on Xilinx IP for memory and other high-speed I/O interfaces, which follow specific rules for clocking.