Required Information for Pin Assignment - 2021.1 English

Versal ACAP Board System Design Methodology Guide (UG1506)

Document ID
UG1506
Release Date
2021-08-04
Version
2021.1 English

For the tools to work effectively, you must provide as much information about the I/O characteristics and topologies as possible. You must specify the electrical characteristics, including the I/O standard, drive, slew, and direction of the I/O.

You must also take into account all other relevant information, including connectivity, clock topology, and timing constraints. Clocking choices in particular can have a significant influence on pinout selection and vice versa.

For IP that have I/O requirements, such as transceivers, PCIe® cores, memory interfaces, and high-speed I/O interfaces, you must configure the IP prior to completing I/O pin assignment. For more information on specifying the electrical characteristics for an I/O, see this link in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).

Important: Not all I/O can reach the PL region in Versal devices, such as some I/O in the corner banks. For more information, see the Versal ACAP Clocking Resources Architecture Manual (AM003), Versal ACAP SelectIO Resources Architecture Manual (AM010), and Versal ACAP Packaging and Pinouts Architecture Manual (AM013).