Types of Vivado Design Suite Projects for I/O Planning - 2021.1 English

Versal ACAP Board System Design Methodology Guide (UG1506)

Document ID
UG1506
Release Date
2021-08-04
Version
2021.1 English

You can perform I/O planning with either of the following types of projects:

I/O planning project
An I/O planning project is an easy entry point that allows you to specify select I/O constraints and generate a top-level RTL file from the defined pins.
Recommended: For Versal devices, only low performance I/O logic interfaces are supported in an I/O planning project. Therefore, Xilinx recommends using an RTL project and the Xilinx IP cores that support high performance XPHY logic.
RTL project
An RTL project allows synthesis and implementation, which enables more comprehensive design rule checks (DRCs). An RTL project also allows generation of IP cores, which is important for memory interface pinout planning, high performance XPHY Logic, and any cores using GTs.

You can run more comprehensive DRCs on a post-synthesis netlist. The same is true after implementation and PDI generation. Therefore, Xilinx recommends using a skeleton design that includes clocking components and some basic logic to exercise the DRCs. This builds confidence that the pin definition for the board will not have issues later.

The recommended signoff process is to run the RTL project through to PDI generation to exercise all the DRCs. However, not all design cycles allow enough time for this process. Often the I/O configuration must be defined before you have synthesizable RTL. Although the Vivado tools enable pre-RTL I/O planning, the level of DRCs performed are fairly basic. Alternatively, you can use a dummy top-level design with I/O standards and pin assignments to help perform DRCs related to banking rules.