Power Design Manager Resource Tabs - 2021.1 English

Power Design Manager User Guide (UG1556)

Document ID
UG1556
Release Date
2021-11-19
Version
2021.1 English

After you have entered the required clock for the design, the remaining resources must be estimated. PDM displays the available resources in a tab on the slide view under the Estimation section.

Figure 1. Power Design Manager Resources

Power Tip: For fast navigation, each tab can be expanded using the > icon and you can jump to the desired table by selecting from the displayed list. For example, clicking to select VCU automatically jumps to the PS & VCU tab to display the VCU table.

PDM organizes resources into the following categories:

PS & VCU
This shows the Processing Subsystem with the MPSoC Processing Subsystem (PS) which has quad-core Arm® Cortex-A53 and dual-core Arm Cortex®-R5F along with a Mali 400 MP GPU. The Video Codec Unit (VCU) and System Monitors can be configured on this tab.
Clock
As described above, this allows you to enter external and internal clocks as well as the PLL and MMCMs that will be used. All clocks generated on this tab can be selected from the other tabs to ensure the clock fanout and therefore power estimation is accurate.
Logic
This tab allows you to enter the logic resource usage and toggle rates. The available K26 SOM resources and usage are displayed in the utilization table.
Figure 2. Logic

Block RAM and URAM
Allows the block RAM and URAM utilization to be entered.
DSP
The K26 SOM has up to 1248 DSP slices available. The utilization along with the clock rate and expected toggle can be entered here.
I/O
The I/O tab, lists all of the available interfaces from both the processing subsystem (DDR4, PSMIO, and GTR) and the PL (PL IOs, and GTHs). The Power Summary & Utilization table shows the available interfaces based on the Kria K26 SOM and the 2 x 240 pin connectors to ensure that designs are kept within the K26 SOM limits.
Figure 3. IO Power Summary and Utilization

For the programmable logic (PL) I/Os, the Kria K26 SOM gives access to six banks 3x HD and 3x HP. PDM allows selection of both VCCO voltage for each of these banks as well as the supported I/O standards that correspond to the VCCO voltage selected.

Figure 4. Programmable Logic for IOs

The previous image shows that you can only select 1.8V IOSTANDARDs based on the 1.8V entered for the HDC VCCO. The power estimated for the PL I/Os will also be reflected as a carrier card current and voltage requirement as these VCCOs need to be provided by the user. The VCCO voltage range is also displayed.

Figure 5. Voltage and Current Requirements

Hard Blocks
This tab allows definition of the desired PCIe setup.
Figure 6. PCIe Block Power Estimation
Power Tip: For drop-down selectable options, pressing the Delete key twice on the cell will reset it back to the default state.