Power Estimation - 2021.1 English

Unassigned clocks and high fanout nets in the logic tab have no clocks

When importing from Vivado® Report Power, logic that does not have an associated clock or any high fanout nets are listed separately. These typically are associated with the highest frequency clock in the design and typically there are very few of these resources. When importing to PDM, they will be listed in the logic tab but have no clocks associated with them as shown in the following figure:

Figure 1. Logic Tab

To resolve, select the appropriate clock from the drop-down or create the required clock in the clock tab and select it for these entries. The power impact of these is typically very low <50 mW. To fully resolve this issue, you should refer to the implemented Vivado design and ensure that these nets are correctly constrained.

Errors flagged in PDM

Import issues are flagged as errors in the respective PDM tab, the most common import issue is the mismatch in the programmable logic IO settings. In the following figure, the IO tab has an error indicator beside it:

Figure 2. Errors flagged in PDM

In the IO tab the error is shown in the specific cell and can be corrected by selecting the correct setting:

Figure 3. IO Tab

DSP Slice Import Always has the Mult Enabled

When importing a .xpe file, the MULT is also imported and this adds a small amount of power to the estimate, the range is up to 40 mW for every 100 DSP slices. This is dependent on the clock rate of the DSP slices and it is typically lower. The following figure shows an example of 100 DSP slices running at 450 MHz and 250 MHz, the power increase from the Mult being enabled is 40 mW@450 MHz → 18 mW@200 MHz.

Figure 4. DSP Slice Import

Figure 5. PS-GTR Table

Using the delete key twice removes an interface, however the power associated with it remains:

Figure 6. Associated PS-GTR Power

To correct this behavior, saving the PDM project and then reopening it allows you to remove power.