Check HDL syntax in the supplied fileset or active fileset.
Syntax
check_syntax [‑fileset <arg>] [‑return_string] [‑quiet] [‑verbose]Usage
| Name | Description |
|---|---|
[-fileset]
|
Fileset to check for syntax |
[-return_string]
|
Return the syntax check messages as a string |
[-quiet]
|
Ignore command errors |
[-verbose]
|
Suspend message limits during command execution |
Categories
Description
Parses Verilog, SystemVerilog, and VHDL source files and generates syntax warnings and error messages for the design.
Tip: The syntax is also checked automatically as the file is edited in the Vivado text editor, or when the file is saved.
This command returns warnings or errors related to the files it examines, or returns nothing if no problems are found.
Arguments
-fileset <arg> - (Optional) Check the syntax of files in the specified fileset.
-return_string - (Optional) Directs the output to a Tcl string rather than to the standard output. The Tcl string can be captured by a variable definition and parsed or otherwise processed.
-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the
set_msg_config command.Examples
The following example checks the syntax of files in the simulation fileset:
check_syntax -fileset sim_1