Embedded Processor Design - 2021.1 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID
UG892
Release Date
2021-07-14
Version
2021.1 English

A slightly different tool flow is needed when creating an embedded processor design. Because the embedded processor requires software in order to boot-up and run effectively, the software design flow must work in unison with the hardware design flow. Data hand-off between the hardware and software flows, and validation across these two domains is critical for success.

Creating an embedded processor hardware design involves the IP integrator of the Vivado Design Suite. In a Vivado IP integrator block design, you instantiate, configure, and assemble the processor core and its interfaces. The IP Integrator enforces rules-based connectivity and provides design assistance. After it is compiled through implementation, the hardware design is exported to Xilinx Vitis™ for use in software development and validation. Simulation and debug features allow you to simulate and validate the design across the two domains.

The Vitis Design Suite is Xilinx's unified software suite that includes compilers for all embedded applications and accelerated applications on Xilinx platforms. Vitis supports developing in higher level languages, leverages open source libraries, and supports domain specific development environments.

Video: For training videos on the Vivado IP integrator and the embedded processor design flow, see the Vivado Design Suite QuickTake Video: Targeting Zynq Devices Using Vivado IP Integrator.

The embedded processor design flow is described in the following resources:

  • Vivado Design Suite User Guide: Embedded Processor Hardware Design (UG898)
  • Vivado Design Suite Tutorial: Embedded Processor Hardware Design (UG940)
  • UltraFast Embedded Design Methodology Guide (UG1046)