Opening an Elaborated RTL Design - 2021.1 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID
UG892
Release Date
2021-07-14
Version
2021.1 English

When you open an elaborated design, the Vivado Design Suite expands and compiles the RTL netlist and applies physical and timing constraints against a target part. The different elements of the elaborated design are loaded into memory, and you can analyze and modify the elements as needed to complete the design. For more information, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).

The Vivado Design Suite includes linting DRCs and checking tools that enable you to analyze your design for logic correctness. You can make sure that there are no logic compilation issues, no missing modules, and no interface mismatches. In the Messages window, you can click links in the messages to display the problem lines in the RTL files in the Vivado IDE Text Editor. In the Schematic window, you can explore the logic interconnects and hierarchy in a variety of ways. The Schematic window displays RTL interconnects using RTL-based logic constructs. You can select logic in the Schematic window and see specific lines in the RTL files in the Vivado IDE Text Editor. For more information, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).

Note: There is no FPGA technology mapping during RTL elaboration.

Constraints that are defined on specific logic instances within the logic hierarchy, such as registers, might not be resolvable during RTL elaboration. The logic names and hierarchy generated during elaboration might not match those generated during synthesis. For this reason, you might see constraint mapping warnings or errors when elaborating the RTL design, if you have these types of constraints defined. However, when you run synthesis on the design, these issues are resolved.

Using the I/O planning capabilities of the Vivado IDE, you can interactively configure and assign I/O Ports in the elaborated RTL design and run DRCs. When possible, it is recommended that you perform I/O planning after synthesis. This ensures proper clock and logic constraint resolution, and the DRCs performed after synthesis are more extensive. For more information, see Vivado Design Suite User Guide: I/O and Clock Planning (UG899).

Tip: When you select the Report DRC command, the Vivado IDE invokes a set of RTL and I/O DRCs to identify logic issues such as asynchronous clocks, latches, and so forth. For more information, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).

To open an elaborated design, use one of the following methods:

  • In the RTL Analysis section of the Flow Navigator, select Open Elaborated Design.
  • In the Flow Navigator, right-click RTL Analysis, and select New Elaborated Design from the popup menu.
  • Select Flow > Open Elaborated Design.

The following figure shows the default view layout for an open elaborated RTL design. Notice the logic instance that was cross-selected from the schematic to the specific instance in the RTL source file and within the elaborated RTL netlist.

Figure 1. Elaborated RTL Design View Layout