Running Timing Analysis - 2021.1 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID
UG892
Release Date
2021-07-14
Version
2021.1 English

The Vivado IDE provides a graphical way to configure and view timing analysis results. You can experiment with various types of timing analysis parameters using Tools > Timing commands. You can use the Clock Networks and Clock Interaction report windows to view clock topology and relationships. You can also use the Slack Histogram window to see an overall view of the design timing performance. For more information, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

In addition, the Vivado IDE has many timing analysis options available through the Tcl Console and SDC constraint options. Many standard report Tcl commands are available to provide information about the clock structure, logic relationships, and constraints applied to your design. For more information, see the Vivado Design Suite Tcl Command Reference Guide (UG835), or type help report_*.