Timing Simulation - 2021.1 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID
UG892
Release Date
2021-07-14
Version
2021.1 English

Xilinx supports timing simulation in Verilog only. You can export a netlist for timing simulation from an open synthesized or implemented design using the File > Export > Export Netlist command in the Vivado IDE, or by using the write_verilog Tcl command.

The Verilog system task $sdf_annotate within the simulation netlist specifies the name of the standard delay format (SDF) file to be read for timing delays. This directive is added to the exported netlist when the -sdf_anno option is enabled on the Netlist tab of the Simulation Settings dialog box in the Vivado IDE. The SDF file can be written with the write_sdf command. The Vivado simulator automatically reads the SDF file during the compilation step.

Tip: The Vivado simulator supports mixed-language simulation, which means that if you are a VHDL user, you can generate a Verilog simulation netlist and instantiate it from the VHDL test bench.

Many users do not run timing simulation due to high run time. However, you should consider using full timing simulation because it is the closest method of modeling hardware behavior. If your design does not work on hardware, it is much easier to debug the failure in simulation, as long as you have a timing simulation that can reproduce the failure.

If you decide to skip timing simulation, you should make sure of the following:

  • Ensure that your STA constraints are absolutely correct. Pay special attention to exceptions.
  • Ensure that your netlist is exactly equivalent to what you intended through your RTL. Pay special attention to any inference-related information provided by the synthesis tool.