After synthesis or implementation, you can perform netlist simulation in functional or timing mode. The netlist simulation can also help you with the following:
- Identify post-synthesis and post-implementation functionality changes caused by:
- Synthesis attributes or constraints that create mismatches (such as full_case and parallel_case)
- UNISIM attributes applied in the Xilinx Design Constraints (XDC) file
- Differences in language interpretation between synthesis and simulation
- Dual-port RAM collisions
- Missing or improperly applied timing constraints
- Operation of asynchronous paths
- Functional issues due to optimization techniques
- Sensitize timing paths declared as false or multi-cycle during STA
- Generate netlist switching activity to estimate power
- Identify X state pessimism
For netlist simulation, you can use one or more of the libraries shown in the following table.
|Library Name||Description||VHDL Library Name||Verilog Library Name|
|UNISIM||Functional simulation of Xilinx primitives||UNISIM||UNISIMS_VER|
|UNIMACRO||Functional simulation of Xilinx macros||UNIMACRO||UNIMACRO_VER|
|UNIFAST||Fast simulation library||UNIFAST||UNIFAST_VER|
The UNIFAST library is an optional library that you can use during functional simulation to speed up simulation runtime. UNIFAST libraries are supported for 7 series devices only. UltraScale and later device architectures do not support UNIFAST libraries, because all the optimizations are incorporated in the UNISIM libraries by default. For more information on Xilinx simulation libraries, see this link in the Vivado Design Suite User Guide: Logic Simulation (UG900).
Primitives/elements of the UNISIM library do not have any timing information except the clocked elements. To prevent race conditions during functional simulation, clocked elements have a clock-to-out delay of 100 ps. Waveform views might show spikes and glitches for combinatorial signals, due to lack of any delay in the UNISIM elements.