You can use an I/O planning project for device exploration and for planning the device pinout for an in-progress system-level design. You can create this type of project prior to completing the HDL or the synthesized netlist. For example, this allows you to exchange design information with the system-level or PCB designer. For more information about I/O planning, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).
- Follow the steps in Creating a Project.
- In the Project Type page, select I/O Planning Project, and click Next.
- Optional: In the Import Ports dialog box, use the following options to select a
file for importing I/O Port definitions and constraints, and click Next.
Note: Use an RTL project to perform I/O pin planning on a design using RTL header or source files.Figure 1. New Project Wizard—Import Ports Page
- Import CSV
- Selects a CSV file with I/O Ports definitions. For more information on CSV files, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).
- Import XDC
- Selects an XDC with I/O Port-related constraints only.
- Do not import I/O ports at this time
- Creates an empty project. You can create or import I/Os later.
- In the Default Part page, select a Xilinx part or TDP board, and click
- Lists available devices. Information about the device resources displays in a table view. You can filter the list using the Product Category, Family, Sub-Family, Package, Speed Grade, and Temp Grade filters. You can also use the Search field to find specific devices
- Lists available TDP boards, and the Xilinx part used on the board. Information about device resources displays in a table view, such as I/O pin count, the number of LUTs and flip-flops, and available block RAM. You can filter the list using the Vendor, Display Name, and Board Rev filters. You can also use the Search field to find specific board parts.
- In the New Project Summary page, review the options you selected to define the project, and
click Finish to create and open the project. Note: For more information on Memory IP I/O planning, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).