You can import an existing RTL-level project file created outside of the Vivado IDE, for example, using Synopsys Synplify, XST, or ISE Design Suite Project Navigator. The Vivado IDE detects the source files in the specified project and automatically adds the files to the new project. Settings such as top module, target device, and VHDL library assignment are imported from the existing project.
- Follow the steps in Creating a Project.
- In the Project Type page, select Imported Project, and click Next.
- In the Import Project page, use the following options to specify the project
file to import, and click Next.
- Imports the specified Xilinx ISE Design Suite (.xise extension) project file.
- Imports the specified Synplify (.prj extension) project file.
- Imports the specified XST (.xst extension) project file.
- Copy Sources into Project
- Copies files into the local project directory instead of referencing the original files.
- In the New Project Summary page, review the options that define the project, and click
Finish. Note: The target part for the project is defined with the settings of the imported project.
The Vivado IDE imports the RTL source files and constraint files from the specified project, and creates a project file in the specified directory. The Vivado IDE writes a summary of the import process to the Import Summary Report log file in the new project directory. In this summary file, you can review the steps used in creating the project as well as any errors or warnings.