The Vivado IDE also includes a logic analysis feature that enables you to perform in-system debugging of the post-implemented design an FPGA device. The benefit of in-system debugging is that you are able to debug a timing-accurate, post-implemented design in the actual system environment at system speeds. The limitations of in-system debugging includes somewhat lower visibility of debug signals compared to using simulation models and potentially longer design, implementation, and debug iterations, depending on the size and complexity of the design.
The Vivado IDE provides several different ways to debug your design. You can use one or more of these methods to debug your design, depending on your needs. For more information, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).