An IP integrator block design can be instantiated into the hierarchy of an HDL design, or it can be defined as the top-level of the design hierarchy.
To integrate the block design into an existing design hierarchy, open the HDL wrapper for the block design. The HDL wrapper, or instantiation template for the block design is created when you generate the output products. The HDL wrapper provides a Verilog module declaration, or VHDL entity declaration for the block design, and creates an instance of the block design module in the wrapper. You can edit the instance definition in the HDL wrapper and cut and paste it into the design hierarchy as needed.
The HDL wrapper can also be used to define the block design as the top-level of the design. For more information see this link in the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994).