An instantiation template is created when you customize and IP and add it to your design or project, regardless of whether you generated output products. The instantiation template provides a Verilog or VHDL instance declaration (.veo or.vho) that you can copy and paste into your RTL design hierarchy.
- Open the instantiation template in the Vivado IDE Text Editor.
- Select the instance declaration in the template file, and copy and paste it into the appropriate source file.
- Edit the signal names on the port definitions to connect to the appropriate signal names in your design.
- You can repeat this process to create multiple instances of the IP core in your design.
After you instantiate the IP in your design, the IP core shows in the Hierarchy tab of the Sources window as integrated into the design. The IP can now be synthesized or simulated as part of the overall design, or separately in the out-of-context flow.