Post-Synthesis Projects - 2021.1 English

Vivado Design Suite User Guide System-Level Design Entry (UG895)

Document ID
UG895
Release Date
2021-06-16
Version
2021.1 English

You can create projects using synthesized netlists created using Vivado synthesis, XST, or any supported third-party synthesis tool. For example, the Vivado Design Suite can import EDIF, NGC, or structural Verilog format netlists, XCI files (all output products including the DCP must be already generated), as well as Vivado design checkpoint (DCP) files. The netlist can be made up of a single file that is all-inclusive or a set of files that are hierarchical and consist of multiple, module-level netlists.

Important: NGC format files are not supported in the Vivado Design Suite for UltraScale devices. It is recommended that you regenerate the IP using the Vivado Design Suite IP customization tools with native output products. Alternatively, you can use the NGC2EDIF command to migrate the NGC file to EDIF format for importing. However, Xilinx recommends using native Vivado IP rather than XST-generated NGC format files going forward.

You can analyze and simulate the netlist logic, launch and manage various implementation runs, and analyze the placed and routed design. You can also experiment with different constraints or implementation strategies.

Recommended: Always reference the Vivado IP using the XCI or XCIX file. Xilinx does not recommend reading just the IP DCP file. While the DCP does contain constraints, it does not provide other output products that an IP could deliver and that could be needed, such as ELF, COE, and Tcl scripts.
Note: ISE IP is only supported for 7 series devices. ISE format IP NGC (.ngc) are no longer supported with UltraScale devices. Users should migrate their IP to native Vivado format prior to beginning UltraScale designs.
Note: When you import an NGC or EDIF file with embedded timing constraints, the constraints are not used by the Vivado Design Suite. Design constraints must be formatted as XDC commands. For information on creating Xilinx design constraints (XDC) files, see Vivado Design Suite User Guide: Using Constraints (UG903). For information on converting user constraints files (UCF) to XDC constraints, see ISE to Vivado Design Suite Migration Guide (UG911).