You can use the Vivado Design Suite to manage the entire design flow from RTL creation through bitstream generation. You can add RTL source files, IP from the Xilinx IP catalog, block designs created in the Vivado IP integrator, digital signal processing (DSP) sources, and EDIF netlists for hierarchical modules. IP can include XCI or XCIX files generated by the Vivado tools, legacy XCO files generated by the CORE Generator tool, and precompiled EDIF or NGC-format netlists. For more detailed RTL information see Elaborating the RTL Design.
From an RTL project, you can elaborate and analyze the RTL to ensure proper syntax and design constructs, launch and manage various synthesis and implementation runs, and analyze the design and run results. You can also experiment with different constraints or implementation strategies to achieve timing closure.