Netlist I/O Planning - 2021.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

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2021.1 English

You can also perform I/O planning with a synthesized netlist. With this method, you use either a synthesized RTL project or a netlist project created with a post-synthesis netlist. Whenever possible, use a synthesized design to perform I/O and clock planning. The Vivado tools have more information about the design after synthesis, and you can use automatic I/O placement and interactive placement modes to control I/O port assignment. You can also use the I/O Planning view layout to see the relationship between the physical pins of the device package and the die pads of the I/O banks on the device.

Using a synthesized design also enables you to make more informed decisions when optimizing the connectivity between the PCB and the Xilinx device. This allows you to better interface with the PCB or system-level designer, making it easier to incorporate IO placement from IP cores that assign I/O placement, like MIPI or the Memory IP. In addition, because all clocks, including generated clocks, are defined after synthesis, the Vivado Design Suite has greater visibility into the clocking requirements and resource utilization and can perform a more thorough validation of the design.

Note: You can perform netlist-based I/O planning on a synthesized RTL design or on a

post-synthesis netlist project. For information on creating a post-synthesis project, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).

Recommended: To check clock logic, Xilinx recommends validation with a synthesized design. To check clock timing, Xilinx recommends validation with an implemented design.