Compilation Options - 2021.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2021-06-16
Version
2021.1 English

The Compilation tab defines and manages compiler directives, which are stored as properties on the simulation fileset and used by the xvlog and xvhdl utilities to compile Verilog and VHDL source files for simulation.