Supported Features - 2021.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2021-06-16
Version
2021.1 English
Table 1. Supported features of VHDL 2008 (IEEE1076-2008)
Features Example/Comment
VHDL-2008 STD and IEEE packages precompiled, including new fixed and float packages, unsigned bit etc.

Limited by other language features such as generic package which XSIM does not yet support. Not all newly added std functions are supported.

Notably, stop and finish are supported.

Simplified sensitivity list process(all)
Matching Relational Operators

?=, ?/=, ?>, ?>=, ?<, ?<=

x ?= y

Unary Reduction Logic Operators
signal x: std_logic_vector(0 to 31);
signal x_and : std:logic;
...
x_and <= and x;
Simplified Case Statement
case x and y is
    when '1' => report "1";
    when '0' => report "0";
end case;

Instead of an intermediate variable or signal, we can use an expression directly in the case statement.

Array / Bit Logic Operators
signal s : std_logic;
signal v, r : std_logic_vector(0 to 7);
...
r <= s and v;
Array / Bit Addition Operators Library functions
Enhanced Bit String Literals

16SX"FF” = "1111_1111_1111_1111”

16UX”FF” = “0000_0000_1111_1111”

Conditional and selected sequential statements
process(clk)
...
    with x select
        y := "111" when "110",
            "000" when others;
    a := '1' when b = '1' else
        '0' when b = '0';
...
Protected type
type areaOfSquare is protected
    procedure setx(newx : real);
    impure function area return real;
end protected;

type areaOfSquare is protected body
variable x : real = 0.0;
...

Protected type shared variable is supported in HDL simulation, but Tcl and GUI does not allow examining value of protected type shared variables yet.

Keyword 'parameter' in procedure declaration procedure proc parameter (a : in std_logic)
Array element resolution function in subtype definition
type bit_word is array (natural range <>) of bit;
function resolve_array (s : bit_word) return bit;
subtype resolved_array is (resolve_array) bit_word;
Block comments
/*
X <= 1;
process(all)
...
*/
Predefined array types boolean_vector, integer_vector etc.
Type passed as Generic
Sentity test is
    generic (type data_type);
    port (
        x : in data_type;
        s : out data_type);
end entity test;
Hierarchical references to signal <<signal .top.dut_inst.sig1 : std_logic_vector(3 downto 0)>>
Expression in port map  
Reading output port  
Max and Min operator  
Matching case statement  
Shift operators (rol, ror, sll, srl, sla and sra)  
Mixing array and scalar logical operators  
Conditional sequential assignments on signal  
Case generate  
Extensions to globally static and locally static expressions  
Static ranges and integer expressions in range bound  
Other features that are not mentioned in the above table, are not supported by Vivado simulator.