Verilog Search Order - 2021.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2021-06-16
Version
2021.1 English

The xelab command uses the following search order to search and bind instantiated Verilog design units:

  1. A library specified by the 'uselib directive in the Verilog code. For example:
    module
    full_adder(c_in, c_out, a, b, sum)
    input c_in,a,b;
    output c_out,sum;
    wire carry1,carry2,sum1;
    `uselib lib = adder_lib
    half_adder adder1(.a(a),.b(b),.c(carry1),.s(sum1));
    half_adder adder1(.a(sum1),.b(c_in),.c(carry2),.s(sum));
    c_out = carry1 | carry2;
    endmodule
  2. Libraries specified on the command line with -lib|-L switch.
  3. A library of the parent design unit.
  4. The work library.