Vivado Simulator VHDL Data Format

Vivado Simulator VHDL Data Format - 2021.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID

UG900

Release Date

2021-06-16

Version

2021.1 English

This section describes how to convert between VHDL values and the format of the memory buffers to use with the XSI functions xsi_get_value and xsi_put_value.