Logic optimization conservatively inserts global clock buffers on clock nets and high-fanout non-clock nets such as device-wide resets. In Versal devices BUFG_FABRIC clock buffers are inserted on high-fanout non-clock nets.
For 7 series designs, clock buffers are inserted as long as 12 total global clock buffers are not exceeded.
For UltraScale, UltraScale+, and Versal designs, clock buffers are inserted as long as 24 total global clock buffers are not exceeded, not including BUFG_GT buffers.
For non-clock nets:
- The fanout must be above 25,000.
- The clock period of the logic driven by the net is below a device/speed grade specific limit.
For fabric-driven clock nets, the fanout must be 30 or greater.
Note: To prevent BUFG Optimization on a net, assign the value NONE to the CLOCK_BUFFER_TYPE property of the net. Some clock buffer insertion that is required to legalize the design can also occur in mandatory logic optimization.