Overview - 2021.1 English

The Intelligent Design Run for timing closure is an aggressive timing closure implementation run with the sole objective of closing timing. Both power and compile time are not considered, but some power optimizations might be possible with utilization savings. It is split into three stages, as shown in the following simplified diagram.

Figure 1. IDR Overview

The flow is fully automated, and there is no user control over which stages can be run. Before attempting to close timing using IDR, a design should be clean of methodology issues. Run report_methodology and fix or waive all critical warnings and warnings.

The details of each of the stages are as follows.

Stage 1: Design Optimization

The Design Optimization stage must always be run. The process of generating and applying suggestions in this stage can result in up to four times the compile time of a standard implementation run. The reasons for this are as follows:

• To generate accurate data for analysis, the implementation tools must be run to post-place or post-route. To apply the suggestions, the design run must be reset and the implementation tools rerun.
• By allowing the impact of QoR suggestions to be realized before conducting a new analysis and generating new suggestions, the impact of design issues is not overestimated, resulting in the maximum QoR impact.

Stage 2: Tool Option Exploration

This stage uses ML strategies to predict the best tool options to use. The flow might exit before this stage if no ML strategies are generated. This stage can be skipped if the design meets criteria for entering the last mile stage (WNS ≥ -0.050 ns and WHS ≥ 0.000). To ensure the best chance of closing timing, the criteria to enter the Last Mile Timing Closure stage are tighter when entering directly from stage 1 (Design Optimization).

Stage 3: Last Mile Timing Closure

This stage leverages post-route phys_opt_design, incremental implementation in timing closure mode, and incremental QoR suggestions to close timing. To enter this stage, a design from the previous stage must have WNS > -0.250 ns and WHS ≥ 0.000 ns. If these criteria are not met, this stage is skipped and the flow exits.