Timing Path Details - 2021.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2021-06-30
Version
2021.1 English

The second half of the report provides more details on the cells, pins, ports and nets traversed by the path. It is separated into three sections:

  • Source Clock Path

    The circuitry traversed by the source clock from its source point to the startpoint of the datapath. This section does not exist for a path starting from an input port.

  • Data Path

    The circuitry traversed by the data from the startpoint to the endpoint.

  • Destination Clock Path

    The circuitry traversed by the destination clock from its source point to the datapath endpoint clock pin.

The Source Clock Path and Data Path sections work together. They are always reported with the same type of delay:

  • max delay for setup/recovery analysis
  • min delay for hold/removal analysis

They share the accumulated delay which starts at the data launch edge time, and accumulates delay through both source clock and data paths. The final accumulated delay value is called the data arrival time.

The destination clock path is always reported with the opposite delay to the source clock and data paths. Its initial accumulated delay value is the time when the data capture edge is launched on the destination clock source point. The final accumulated delay value is called the data required time.

The final lines of the report summarize how the slack is computed.

  • For max delay analysis (setup/recovery)
    slack = data required time - data arrival time
  • For min delay analysis (hold/removal)
    slack = data arrival time - data required time