Debug Bridge - 2021.1 English

Vivado Design Suite User Guide Programming and Debugging (UG908)

Document ID
UG908
Release Date
2021-06-16
Version
2021.1 English
Note: The Debug Bridge IP is not supported on Versal architectures.

The Debug Bridge IP core is a controller that provides multiple options to communicate with the debug cores in the design.

The primary use case for a Debug Bridge is to use a Xilinx Virtual Cable (XVC) to remotely debug designs through Ethernet or other interfaces without the need for a JTAG cable.

The other common use case is for debugging Dynamic Function eXchange and Tandem PCIe with Field Updates designs. For more information on the Tandem PCIe with Field Updates flow and Debug Bridge refer to UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).

The Debug Bridge can also be used with the PCIe® core in systems where JTAG is not the preferred communication and debug mechanism. For more information on the using the XVC flow with the PCIe core and Debug Bridge refer to UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).

Detailed documentation on the Debug Bridge core IP can be found in the Debug Bridge LogiCORE IP Product Guide (PG245).