Memory Calibration Debug Tcl Usage - 2021.1 English

Vivado Design Suite User Guide Programming and Debugging (UG908)

Document ID
UG908
Release Date
2021-06-16
Version
2021.1 English

Use the following Tcl commands in the Vivado Tcl Console when connected to the hardware in Vivado Hardware Manager to output all memory calibration debug content that is displayed in the Vivado IDE.

  • get_hw_migs
    • Displays what memory interfaces exist in the design.
  • refresh_hw_mig [lindex [get_hw_migs] 0]
    • Refreshes only the memory interfaces denoted by index (index begins with 0).
  • report_propery[lindex [get_hw_migs] 0]
    • Reports all of the parameters available for the memory interface.
    • Where 0 is the index of the memory interface to be reported (index begins with 0).

    For more specific details see the UltraScale or 7 Series Memory Calibration debug commands in the following documents:

  • Xilinx Answer 43879, MIG 7 Series DDR3/DDR2 - Hardware Debug Guide.
  • UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150)