Using XDC Commands to Insert Debug Cores - 2021.1 English

Vivado Design Suite User Guide Programming and Debugging (UG908)

Document ID
UG908
Release Date
2021-06-16
Version
2021.1 English

In addition to using the Set up Debug wizard, you can also use XDC commands to create, connect, and insert debug cores into your synthesized design netlist. Follow the these steps by typing the XDC commands in the Tcl Console:

  1. Open the synthesized design netlist from the synthesis run called synth_1.
    open_run synth_1
    Important: The XDC commands in the following steps are only valid when a synthesized design netlist is open.
  2. Create the ILA core black box.
    create_debug_core u_ila_0 ila
  3. Set the various properties of the ILA core.
    set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
    set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
    set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
    set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
    set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
    set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
    set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
    set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
  4. Set the width of the clk port of the ILA core to 1 and connect it to the desired clock net.
    set_property port_width 1 [get_debug_ports u_ila_0/clk]
    connect_debug_port u_ila_0/clk [get_nets [list clk ]]
    Note: You do not have to create the clk port of the ILA core because it is automatically created by the create_debug_core command.

    Important: All debug port names of the debug cores are lower case. Using upper-case or mixed-case debug port names will result in an error.
  5. Set the width of the probe0 port to the number of nets you plan to connect to the port.
    Note: You do not have to create the first probe port (probe0) of the ILA core because it is automatically created by the create_debug_core command. set_property port_width 1 [get_debug_ports u_ila_0/probe0]
  6. Connect the probe0 port to the nets you want to attach to that port.
    connect_debug_port u_ila_0/probe0 [get_nets [list A_or_B]]
  7. Optionally, create more probe ports, set their width, and connect them to the nets you want to debug.
    create_debug_port u_ila_0 probe
    set_property port_width 2 [get_debug_ports u_ila_0/probe1]
    connect_debug_port u_ila_0/probe1 [get_nets [list {A[0]} {A[1]}]]

For more information on these and other related Tcl commands, type help -category ChipScope in the Tcl Console of the Vivado Design Suite.