As in a flat flow, bitstreams are created with the
write_bitstream command. For each design configuration, simply issue
write_bitstream to create a full standard
configuration file plus one partial bit file for each RM within that configuration.
Xilinx recommends providing the configuration
name and RM names in the
-file option specified with
write_bitstream. Only the base bit file name can be
modified, so it is important to record which RMs were selected for each
Using the previous design, the following is an example of reading routed checkpoints (configurations) and creating bitstreams for all implemented RMs.
This command generates all possible bitstreams for this particular configuration. It creates a full design bitstream called config1.bit. This bitstream should be used to program the device from power-up and includes the functionality of any RMs contained within. It also creates partial bit files config1_pblock_rp1_partial.bit and config1_pblock_rp2_partial.bit that can be used to reconfigure these modules while the FPGA continues to operate. For UltraScale devices, it creates clearing bitstreams that pair with each partial bitstream, allowing you to prepare the partition for the next partial image. Repeat these steps for each configuration.
The size of each partial bitstream is reported in the output from
write_bitstream. As this command is run, these messages will be reported for each partial and clearing bit file.
Partial bitstream contains 3441952 bits.
Writing bitstream ./Bitstreams/right_up_pblock_inst_shift_partial.bit...
Bitstream compression, encryption, and other advanced features can be used. See Known Limitations for specific unsupported use cases for UltraScale devices.
Generating Partial Bitstreams Only
If the full design configuration file is not required, then a single partial
bitstream can be created on its own. With a full design configuration checkpoint
loaded in memory, use the
-cell option to identify the instance for
which a partial bitstream is needed. The name of this partial bitstream can be
given, as it is not automatically derived from the Pblock name.
write_bitstream -cell rp1 RM_count_down_partial.bit
This creates only a partial bitstream for the RP identified.
write_bitstream directly on RM checkpoints;
only use full design checkpoints. RM checkpoints, while they are placed and routed
submodules, have no information regarding the top level design implementation, and
therefore would create unsuitable partial bit files.
Generating Full Configuration Bitstreams Only
If only power-on design bitstream is desired, the
-no_partial_bitfile option can be used to bypass creation of
write_bitstream -no_partial_bitfile config3
Using this option skips the stage that creates partial and clearing bitstreams. It
write_bitstream runtime for scenarios where either you are
looking to test only the full design without DFX, or if the partial bitstreams
Generating Static-only Bitstreams
If a power-on configuration of the static design only is desired, run
write_bitstream on the checkpoint that has
empty RPs (after
update_design -black_box and
update_design -buffer_ports have run). This
"gray box configuration" can be compressed to reduce the bit file size and