Dynamic Function eXchange is supported using the following configuration modes:
- A good choice for user configuration solutions. Requires the creation of an ICAP controller as well as logic to drive the ICAP interface.
- ( UltraScale™ and UltraScale+™ devices only) Provides a dedicated connection to the configuration engine from one specific PCIe® block per device.
- The primary configuration mechanism for Zynq®-7000 SoC and Zynq UltraScale+ MPSoC designs.
- A good interface for quick testing or debug. Can be driven with the Vivado Logic Analyzer.
- Slave SelectMAP or Slave Serial
- A good choice to perform full configuration and dynamic reconfiguration over the same interface.
Master modes are not directly supported because IPROG housecleaning clears the configuration memory.
|Configuration Mode||7 series||Zynq||UltraScale||UltraScale+||Zynq UltraScale+ MPSoC|
|SPI (any width) 1||No||N/A||No||Yes||N/A|
|BPI sync mode||No||N/A||No||Yes||N/A|
|BPI async mode||Yes||N/A||Yes||Yes||N/A|
To use external configuration modes (other than JTAG) for loading a
partial BIT file, these pins must be reserved for use after the initial device
configuration. This is achieved by using the
BITSTREAM.CONFIG.PERSIST property to keep the dual-purpose I/O for
configuration usage and to set the configuration width. Refer to this link in the
Vivado Design Suite User Guide:
Programming and Debugging (UG908). The Tcl command syntax to set
this property is:
set_property BITSTREAM.CONFIG.PERSIST <value> [current_design]
<value> is either
Partial bitstreams contain all the configuration commands and data necessary for Dynamic Function eXchange. The task of loading a partial bitstream into an FPGA does not require knowledge of the physical location of the RM because configuration frame addressing information is included in the partial bitstream. A valid partial bitstream cannot be sent to the wrong part of the FPGA.
A DFX controller retrieves the partial bitstream from memory, then delivers it to a configuration port. The DFX control logic can either reside in an external device (for example, a processor) or in the programmable logic of the FPGA to be reconfigured. A user-designed internal DFX controller loads partial bitstreams through the ICAP interface. As with any other logic in the static design, the internal DFX control circuitry operates without interruption throughout the reconfiguration process.
Internal configuration can consist of either a custom state machine, or an embedded processor such as MicroBlaze. For a Zynq-7000 SoC and Zynq UltraScale+ MPSoC, the Processor Subsystem (PS) can be used to manage partial reconfiguration events.
As an aid in debugging Dynamic Function eXchange designs and DFX control logic, the Vivado Logic Analyzer can be used to load full and partial bitstreams into an FPGA by means of the JTAG port.
For more information on loading a bitstream into the configuration ports, see the Configuration Interfaces chapter in these documents: