Design Elements Inside Reconfigurable Modules - 2021.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2022-02-25
Version
2021.1 English

Versal devices support partial reconfiguration for almost all component types. Logic that can be placed in a RM includes:

  • NoC Master Units (NMUs) and NoC Slave Units (NSUs)
  • Boundary Logic Interface (BLI) flipflops
  • XPIO and HDIO banks:
    • Includes XPHY, ISERDES, OSERDES, and IDELAYCTRL
  • Memory Controllers:
    • DDRMC and DDRMC_RIU
  • Serial transceivers (MGTs) and related components:
    • GTYE5_QUAD, MRMAC, and PCIE40E5
  • All logic components that are mapped to a CLB slice:
    • LUTs (look-up tables), LUTRAMs, FFs (flip-flops), SRLs (shift registers), MUXFs, and LOOKAHEAD.
  • Block RAM:
    • RAMB18E5 and RAMB36E5
  • DSP blocks: DSP48E2
  • PCIe┬« (PCI Express), CMAC (100G MAC), and ILKN (Interlaken MAC) blocks
  • UltraRAM blocks: URAM288E5 and URAM288E5_BASE
  • Clocks and Clock Modifying Logic:
    • Includes BUFG_FABRIC, BUFGCE, BUFG_GT, BUFG_GT_SYNC, BUFGMUX, MMCM, DPLL, XPLL and MBUFG
  • AI Engines
    • Versal AI Engine inclusion in RM is supported through Vitis platform flows only.