- Dynamic Function eXchange requires the use of Vivado 2013.3 or newer.
- Partial Reconfiguration (PR) is supported in the ISE Design
Suite as well. Use the ISE Design Suite for PR only with Virtex-6, Virtex-5
and Virtex-4 devices. See the
Partial Reconfiguration User Guide (v14.5) (UG702) for more information.
- Floorplanning is required to define reconfigurable regions, per element type.
- For 7 series, vertically align Pblocks with frame/clock
region boundaries. This produces the best results and allows
RESET_AFTER_RECONFIG to be enabled.
- For UltraScale and
beyond, the floorplanning is more flexible. Xilinx recommends stopping the Pblock short of frame/clock
region boundaries to allow for expanded routing, which can greatly improve
routability and quality.
- Horizontal alignment rules also apply. See Create a Floorplan for the Reconfigurable Region
for more information.
- Automatic expansion for routing resources is done for all
UltraScale, UltraScale+, and Versal
- Bottom-up/OOC synthesis (to create multiple netlist/DCP files) and management of
RM netlist files is the responsibility of the user.
- For third party synthesis tools, I/O insertion must be
- For Vivado OOC
synthesis, I/O insertion is automatically disabled in the out_of_context
- Standard timing constraints are supported, and additional timing budgeting capabilities are available if needed.
- A unique set of design rule checks (DRCs) has been established to help ensure successful design completion.
- A DFX design must consider the initiation of partial reconfiguration as well as
the delivery of partial BIT or PDI files, either within the target device or as part
of the system design.
- The Vivado Design Suite includes support for
the Dynamic Function eXchange Controller IP. This customizable IP manages the core
tasks for partial reconfiguring any Xilinx
device. The core receives triggers from hardware or software, manages handshaking
and decoupling tasks, fetches partial bitstreams from memory locations, and delivers
them to the ICAP. More information on the DFX Controller IP is available on the
- An RP must contain a super set of all pins to be used by the varying
reconfigurable modules (RM) implemented for the partition. If an RM uses different
inputs or outputs from another RM, the resulting RM inputs or outputs might not
connect inside of the RM. The tools handle this by inserting a LUT1 buffer within
the RM for all unused inputs and outputs. The output LUT1 is tied to a constant
value and the value of the constant can be controlled by
HD.PARTPIN_TIEOFF property on the unused output pin. For more
information on this property refer to Black Boxes
- Black boxes are supported for bitstream generation. See Black Boxes for details about how to tie off ports with constant values.
- For user reset signals, determine if the logic inside the RM is level or edge
sensitive. If the reset circuit is edge sensitive (as it may be in some IP such as
FIFOs), the RM reset should not be applied until after reconfiguration is
designs are compatible with the Xilinx Isolation
Design Flow (IDF) for Zynq MPSoC devices. For more information on
solution details, please consult
Isolation Design Flow for UltraScale+ FPGAs and Zynq
UltraScale+ MPSoCs (XAPP1335).