Similar to previous architectures, the DFX flow in Versal generates scripts in a folder called
hd_visual inside the implementation directory. In addition to placement
and routing footprint, there are few more Tcl scripts generated by Versal DFX flow which can be used for debugging purpose if needed.
Overlapped_AllTiles.tclIn Versal, Interconnect and Clocking tiles can potentially be shared by two reconfigurable partitions. This contains the list of tiles that are shared by multiple RPs.
RCLKrow is split into two RPs, Pblock that has the top half of RCLK tow corresponds to this TCL. This contains the list of clock tiles that will be programmed during partial PDI download of that RP.
<pblock_name>_bottom_SplitPRTiles.tcl: If RCLK row is split into two RPs, Pblock that has the bottom half of RCLK tow corresponds to this TCL. This contains the list of clock tiles that will be programmed during partial PDI download of that RP.
<pblock_name>_Placement_AllTiles.tcl: All tiles that are in the placement range of the corresponding RP pblock.
<pblock_name>_Routing_AllTiles.tcl: Routing footprint of a reconfigurable pblock will be different from placement footprint. This is because of features like expanded routing and clock routing expansion. This TCL file provides the list of all tiles in the routing footprint of that RP which will be programmed during partial PDI download. Routing footprint will be a superset of placement footprint.Note: Interconnect tiles at the edge of 2 adjacent RPs can be shared by both RPs. However, this situation should be avoided whenever possible as each RP gets only half the routing resources of that interconnect tile causing potential routability issues.It is always advised to avoid adjacent RPs. It is recommended to keep a static shim Pblock between two RPs and assign the static endpoints between 2 RPs into that Pblock.