In UltraScale and UltraScale+ devices, I/O logic and buffers can be included in an RP. While the I/O can be modified from one RM to another, there are some rules that must be followed.
The following checks are done between all configurations that use the I/O sites. If an I/O site changes from being used to unused, or vice versa, then these checks are not done for those configurations. If an I/O is unused in a particular configuration, make sure the appropriate property for the design is set on these ports via the PULLTYPE attribute. For more information on setting PULLTYPE, see this link in Vivado Design Suite Properties Reference Guide (UG912).
- The I/O direction and I/O standard must be the same between all RMs whenever the I/O is used.
DCI_CASCADE, the member bank assignments between RMs cannot overlap.
- Legal example: In Configuration 1,
DCI_CASCADEhas banks 12, 13. In Configuration 2,
DCI_CASCADEhas banks 14, 15 and 16. They do not have overlapped banks.
- Illegal example: In Configuration 1,
DCI_CASCADEhas banks 12 and 13. In Configuration 2,
DCI_CASCADEhas banks 13, 14, 15 and 16. In this case bank 13 overlaps.
- Legal example: In Configuration 1,
DCI_CASCADE, member banks must be fully contained within the reconfigurable region. All of the member banks for the same
DCI_CASCADEmust be in either the same RP Pblock, or completely in static.
DCI_CASCADEusage must remain consistent between different RM.
- DCI calibration is automatically done for any IO bank included in a RP at the end of partial reconfiguration, in the same way it is done at the initial configuration of the device. DCIRESET or any user intervention is not necessary.
Changes to the IOB from one configuration to another are limited by the rules above. This means that the following I/O characteristics may be modified through Dynamic Function eXchange:
- Usage (used vs. unused, per I/O)
- Drive Strength (12 mA, 8 mA, etc.)
- Driver Output Impedance (40Ω, 48Ω, etc.)
- Driver Input Impedance (40Ω, 48Ω, etc.)
- Driver Slew Rate (slow, fast, etc.)
- ODT Termination (40, 60, etc.)
Adding the I/O sites into the RP requires that the entire PU (encompassing the I/O bank, BITSLICE, MMCM, PLL, and one column of CLBs plus shared interconnect) be added. All components in this fundamental region are reconfigured and reinitialized, and adding these other site types to the reconfigurable region can be beneficial in some cases for these reasons:
- Adding I/O sites allows use of the routing resources of the I/O, which reduces congestion (instead of increasing congestion, as it could if the I/O sites were in Static, and caused a gap in the reconfigurable region).
- Allows reconfiguration of other clocking resources like the MMCM and PLL.
- Allows reconfiguration of other I/O logic sites such as BITSLICE and BITSLICE_CONTROL.
Regardless of whether or not the I/O usage or characteristics change during reconfiguration, the entire bank is reconfigured. During reconfiguration, all I/O in the banks defined by the RP Pblock is held with the dedicated global tri-state (GTS) signal, which is released at the end of reconfiguration.
If the RM contains an MMCM or PLL component, the size of the partial bitstream will be at its smallest when the lock cycle of these components are set to "no wait". Similarly, IO with DCI matching requirements will have minimal bitstream sizes when the lock cycle is set to “no wait”. Set these options using this commands:
set_property BITSTREAM.STARTUP.LCK_CYCLE NoWait [current_design] set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]
During the Dynamic Function eXchange flow, RMs are carved out using
update_design -black_box. During this command any embedded IO buffers, and the associated constraints, such as
IOSTANDARD, are removed. When the black box RP is filled in with a new RM, these IOB constraints need to be reapplied to the design.