- MBUFGCE primitives not allowed for boundary clock nets.
- MBUFG primitives in Versal allows clock division at the leaf level to reduce
clock track utilization and improve timing closure on synchronous CDCs. For
DFX designs, MBUFG optimization is allowed only for static clock nets or
internal RM clock nets. Boundary clock nets can continue to use
BUFGCE_DIV/MMCM/PLL clocking primitives for clock division. However, this
will have reduced QoR benefits compared to using MBUFG primitives since
latter provides common clock node closer to loads at the leaf level. Hence
it is recommended to use MMCM/PLL inside partitions of the DFX design to
convert a boundary clock net to internal clock net which can leverage MBUFG
optimizations of Vivado.
- Restrictions in clock resource usage due to clock tile splitting.
- When clock tile is shared between multiple RPs, it is possible that some of
the nodes cannot be used for clock routing. To avoid potential unroutability
because of tile splitting, DFX flow automatically prohibits usage of few
clocking tiles. To avoid this scenario, Xilinx recommends keeping at least
one clock region wide gap between multiple RP pblocks if utilization
estimation meets the design need.