Because the reconfigurable logic is modified while the device is operating, the static logic connected to outputs of RM ignores the data from RM during partial reconfiguration. The RMs do not provide valid output data until partial reconfiguration is complete and the reconfigured logic is reset. It is not possible to predict or simulate the functionality of the RM. Logical decoupling isolates the dynamic part of the design from the static, ensuring no unintended activity disrupts the static design.
There are number of boundary types where logical decoupling should be inserted, based on the connectivity of the RP, and there are different strategies for each scenario. A boundary could be within the PL, within the NoC, at the PS-PL interface, or a RP could have interface ports in each of these categories.
Decouple at the PL Boundary
A common design practice to mitigate this issue is to register all output signals (on the static side of the interface) from the RP. An enable signal is used to isolate the logic until it is completely reconfigured. Other approaches include a simple 2-to-1 MUX on each output port, or to higher level bus controller functions.
Two pieces of IP are available from Xilinx to provide decoupling capabilities in the PL. First, the DFX Decoupler IP allows user to insert muxes to easily and efficiently decouple AXI4-Lite, AXI4-Stream, and custom interfaces. This IP simply disables key signals to prevent unwanted activity on the RP boundary. Second, the DFX AXI Shutdown Manager IP <to fill>. More information about the DFX Decoupler IP is available on the Xilinx website.
Decouple in the NoC
If the boundary falls within the NoC, NoC quiescing is automatic only if NMU/NSU is inside RP. If NOC/PL AXI interface is at RM boundary, decoupler is still required. In such case, it is recommended to put the interface NOC in RP to avoid the use of AXI decoupler. Then the connection across partition is not AXI anymore, but NoC internal path through INI.
Decouple at the PS-PL interface
- If the entire PL is included in the dynamic region, partial reconfiguration includes a power domain shutdown such that the entire PL is temporarily powered down.
- The static design should include the functional behavior required for the data and interface management. It can implement mechanisms such as handshaking or disabling interfaces (which might be required for bus structures to avoid invalid transactions). It is also useful to consider the down-time performance effect of a dynamic module (that is, the unavailability of any shared resources included in the dynamic module during or after reconfiguration). This is the most common scenario.