Nested Dynamic Function eXchange (Nested DFX) is the concept of placing one or more dynamic regions within a dynamic region, subdividing a device to permit more granular reconfiguration. With this feature, you can segment a RP into smaller regions, each of which is partially reconfigurable. This greater depth of flexibility allows for RM of different sizes, shapes, and resource sets to be swapped on the fly. For example, a data center application could load one large RM in a region in a device, or two smaller independent functions in that same region; these two smaller functions could then be individually reconfigured as needed, resulting more efficient use of silicon resources.
While there is no formal limit to the number of levels into which a device may be subdivided, the further you go, the more difficult it will be to place and route. Moreover, the more complex the levels become, the more complex the management of partial bitstreams become. Realistically, most designs on even the largest devices should not exceed three levels of reconfiguration.
Nested DFX in this release is available for UltraScale and UltraScale+ targets, including Zynq UltraScale+ MPSoC and RFSoC devices. Versal support will begin in a future release, after base Dynamic Function eXchange (DFX) support has been added for this family. No 7 series devices will be supported for Nested DFX. Only the Tcl-based non-project flow is supported in this release. Project support, including IP integrator, will be considered in a future release.