Partition Pin Placement - 2021.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2021.1 English

Each pin of an RP has a partition pin (PartPin). By default the tools automatically place these PartPins inside of the RP Pblock range (which is required). For many cases, this automatic placement can be sufficient for the design. However, for timing-critical interface signals or designs with high congestion, it might be necessary to help guide the placement of the PartPins. The following is an example of how to achieve this:

  • Define user HD.PARTPIN_RANGE constraints for some or all of the pins.
    [get_pins <rp_cell_name>/*]

    By default the HD.PARTPIN_RANGE is set to the entire Pblock range. Defining a user range allows the tools to place PartPins in the specified areas, improving timing and/or reducing congestion.

    Important: When examining the placement of PartPins, there are limited routing resources available along the edges, and especially in the corners, of the Pblock. The PartPin placer attempts to spread the partition pins, minimizing the number of partition pins per interconnect along the edges, and increasing the PartPin density towards the middle of the Pblock. When defining a custom HD.PARTPIN_RANGE constraint, be sure to make the range wide enough to allow for spreading, or you are likely to see congestion around the PartPins.