Each module (including Static) needs to be synthesized bottom-up so that a netlist or checkpoint exists for static and each RM.
- Synthesize the top level:
read_verilog top.v (and other HDL associated with the static design, including black box module definitions for RMs), then:
read_xdc top_synth.xdc synth_design -top top -part xc7k70tfbg676-2 write_checkpoint top_synth.dcp
- Synthesize an
read_verilog rp1_a.v synth_design -top rp1 -part xc7k70tfbg676-2 -mode out_of_context write_checkpoint rp1_a_synth.dcp
- Repeat for each remaining
read_verilog rp1_b.v synth_design -top rp1 -part xc7k70tfbg676-2 -mode out_of_context write_checkpoint rp1_b_synth.dcp