This document contains a set of tutorials designed to help you debug complex FPGA designs. The first four labs explain different kinds of debug flows that you can chose to use during the course of debug. These labs introduce the Vivado® Design Suite debug methodology recommended to debug your FPGA designs. The labs describe the steps involved in taking a small RTL design and the multiple ways of inserting the Integrated Logic Analyzer (ILA) core to help debug the design. The fifth lab is for debugging high-speed serial I/O links in the Vivado tool. The sixth lab is for debugging JTAG-AXI transactions in the Vivado tool. The first four labs converge at the same point when connected to a target hardware board.
Example RTL designs are used to illustrate overall integration flows between the Vivado logic analyzer, ILA, and the Vivado Integrated Design Environment (IDE). To be successful using this tutorial, you should have some basic knowledge of the Vivado tool flow.