Using the ECO Flow to Replace Debug Probes Post Implementation - 2021.1 English

Vivado Design Suite Tutorial: Programming and Debugging (UG936)

Document ID
UG936
Release Date
2021-07-14
Version
2021.1 English

This simple tutorial shows you how to replace nets connected to an ILA core in a placed and routed design checkpoint using the Vivado® Design Suite Engineering Change Order (ECO) flow.

Note: To learn more about using the ECO flow, refer to the Debugging Designs Post Implementation chapter in the Vivado Design Suite User Guide: Programming and Debugging (UG908).
  1. Open the Vivado® Design Suite, and select File > Open Checkpoint.

  2. Open the routed checkpoint that you created in Using the HDL Instantiation Method to Debug a Design.

    Change the layout in the Vivado Design Suite toolbar dropdown to ECO.



    Note: The Flow Navigator window now changes to ECO Navigator with a different set of options.


  3. In the ECO Navigator window, click Replace Debug Probes to bring up the Replace Debug Probes dialog box. Note the Debug Hub and ILA cores in the design.

    Important: Xilinx strongly recommends that you do not replace the clock nets associated with ILA and Debug Hub cores.
  4. In the Replace Debug Probes dialog box, highlight the probes whose nets you want to change. In this lab we will replace the GPIO_BUTTONS_dly[0] net that is being probed.
  5. Click the Edit Probes button to the right of the GPIO_BUTTONS_dly[0] probe net to bring up the Choose Nets dialog box.

  6. In the Choose Nets dialog box, choose the U_DEBOUNCE_0/clear net to replace the existing GPIO_BUTTONS_dly[0] probe net. Click OK.

  7. Type for “*clear net” in the Name field and Click Find. Notice the U_DEBOUNCE_0 net in the Found nets area. Select U_DEBOUNCE_0/clear net using the “->” arrow and click OK. The U_DEBOUNCE_0/clear net to replaces the existing GPIO_BUTTONS_dly[0] probe net.



  8. Now click OK in the Replace Debug Probes dialog. An additional dialog box may appear if the nets were marked with DONT_TOUCH indicating that it must be removed to proceed. If so, click Unset Property and Continue.

    Important: Check the Tcl Console to ensure that there are no Warnings/Errors.




  9. Save your modifications to a new checkpoint. Use the Save Checkpoint As option in the ECO Navigator to bring up the Save Checkpoint As dialog box. Specify a file name for the .dcp file and click OK.

  10. Click Write Debug Probes in the ECO Navigator. When the Write Debug Probes dialog appears, click OK to generate a new .ltx file for the debug probes.

  11. Click Generate Bitstream in the ECO navigator. When the Generate Bitstream dialog appears, change the bit file name to project_sinegen_demo_routed_debug_changes.bit in the Bit File field and click OK to generate a new .bit file that reflects the debug probe changes.

  12. Connect to the Vivado Hardware Manager by selecting Open Hardware Manager in the ECO Navigator.
  13. Connect to the local hardware server by following the steps in the Target Board and Server Set Up section in Using the Vivado Logic Analyzer to Debug Hardware.

    Program the device using the .bit file and.ltx files that you created in the previous steps.



  14. Select Window > Debug Probes from the Vivado Design Suite toolbar. Ensure that the probes that were replaced in step 8 and 9 above are reflected in the probes associated with hw_ila_1.

  15. Run the Trigger on the ILA. Ensure the probes that were replaced in step 8 and 9 above are reflected in the Waveform window as well.