Feature Covered - 2021.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2021-07-14
Version
2021.1 English
The following features are covered in the GTM-Wizard:
  1. Detection of designs with PAM4 signals, designs instantiating GTM_DUAL and automatic generation bypass module (xil_dut_bypass).
  2. Simple sanity check for design that should instantiate bypass module.
  3. A mechanism to view PAM4 signals in Waveform Viewer for XSim users.
  4. Provide a way to generate bypass module for export simulation flow.

In this tutorial, we would generate an GTM-Wizard example design, which usage PAM4 signal. To generate that, please follow steps below:

  1. Create project in Vivado 2021.1 without adding source/constraint file Create project > next > next > next > next > next.
  2. In default part, select family Virtex UltraScale+ 58G and select parts as shown in the following figure and click Next.

  3. Check the summary report and click finish.

  4. Under Project Manager, click on IP Catalog and search for gtm_wizard and then double click on block design.

  5. Click Ok on default configuration and click skip on Generate output product pop-up.

  6. On source window, right-click on generated XCI file and click open IP Example Design by specifying location.

    At this stage, you have an example ready to run simulation.

Before heading towards simulation, here are few things from PAM4 point of view:

  1. xil_dut_bypass module definition is generated on run time by tool which contain hierarchical reference to GTM_DUAL.

  2. This xil_dut_bypass module generation is control under switch Configure Design for Hierarchical Access, which is set by default.

    Note: For old behavior, please uncheck Configure Design for Hhierarchical Access.

    Once design is created, we can run it either through launch_simulation or export simulation.

Launch_simulation
  1. Click on Run Behavioral Simulation. This will run simulation with Vivado Simulator (XSim).

  2. Once snapshot is created and loaded, simulation will stop after 1000 ns. Let’s look at xil_dut_bypass definition. Double-click on xil_dut_bypass in scope window to see the source file. Notice the hierarchical reference from Top module till leaf level instance.

  3. Right-click xil_dut_bypass and add to waveform.

  4. Click restart then run all.
  5. Once simulation is complete, section all signal of xil_dut_bypass in waveform, right-click and select waveform style to analog.

  6. Go to analog setting under waveform style and change the value like below for better waveform.

  7. Observe the analog value of signals.

    Note: For running same design with third party simulators, please refer to Vivado Design Suite User Guide: Logic Simulation (UG900)
Export_simulation
The following are the two flows for export simulation:
Export simulation with xil_dut_bypass generated
  1. Invoke command export_simulation -simulator xsim -generate_hier_access on Vivado IDE.
  2. This generates scripts in <your_local_path>/export_sim/xsim.
  3. In the generated vlog.prj, observe xil_dut_bypass.sv. This is because launch_simulation has generated and added this as part of project.

  4. Invoke gtm_wizard_ultrascale_0_example_top_sim.sh it runs the simulation. If you want to run in GUI mode, add -gui to xsim command of else part.
  5. Follow step-3 to step-7 under launch_simulation and you will able to see same waveform/output as launch_simulation.
Export simulation without xil_dut_bypass
  1. Invoke gtm_wizard_ultrascale_0_example_top_sim.sh -gen_bypass.
  2. It runs the simulation for delta time unit and generate hierarchical path in log file.
  3. In generated simulate.log, note down the entry xilinx_hier_bypass_ports:gtm_wizard_ultrascale_0_example_top_sim.u_e….
  4. Generate xil_dut_bypass.sv by invoking generate_hier_access -log ./simulate.log on Vivado TCL console.
  5. Observe xil_dut_bypass.sv generate in current directory.
  6. Add this xil_dut_bypass.sv in vlog.prj as sv xil_defaultlib ./xil_dut_bypass.sv.
  7. Invoke gtm_wizard_ultrascale_0_example_top_sim.sh it runs simulation. If you want to run in GUI mode, add -gui to xsim command of else part.

  8. Follow step-3 to step-7 under launch_simulation and you can see same waveform/output as launch_simulation.
Generating xil_dut_bypass for non-vivado project
  1. Create compile order of the design (<design>.prj).
  2. Execute XSim simulator tools to generate the simulator log file:
    1. xelab -prj <design>.prj -top <testbench-top>.
    2. xsim -R <testbench-top> --testplusarg GEN_BYPASS.
  3. Verify <simulator>.log file generated and that it contains the xilinx_hier_bypass_ports string with the hierarchical path information. For example:
    xilinx_hier_bypass_ports:tb.dut_i.gtmWiz_00.gtm_i in:integer:in1:in_var1 in:integer:in2:in_var2 
    out:integer:out1:out_var1 out:integer:out2:out_var2
  4. Download generate_hier_access.tcl utility from GitHub:
    wget https://raw.githubusercontent.com/Xilinx/XilinxTclStore/2020.1-dev/tclapp/xilinx/projutils/generate_hier_access.tcl
  5. Execute generate_hier_access.tcl to generate the sources for hierarchical access simulation:
    1. # /usr/bin/tclsh.
    2. source generate_hier_access.tcl.
    3. generate_hier_access -bypass dut_bypass -testbench <module> -directory <path> -log <simulator>.log. Instantiate this xil_dut_bypass in test bench with proper connection.
  6. Add <path>/xil_dut_bypass.sv to <design>.prj.
  7. Run simulator tools to simulate the design in <design>.prj.