You can create a non-project script to read a top-level design netlist, the IP, the design constraint files, and then implement the design.
Modify this script accordingly to point to your source file locations.
# Set the target part to be used set_part xc7k70tfbg676-1 # Read top-level EDIF netlist produced by the third party synthesis tool read_edif ./sources/wave_gen.edf # Read the two IP # Read the IP and use any required output products generated (XDC, DCP, etc.) read_ip ./my_ip/char_fifo/char_fifo.xci read_ip ./my_ip/clk_core/clk_core.xci # read top-level constraints read_xdc ./sources/wave_gen_timing.xdc read_xdc ./sources/wave_gen_pins.xdc # Link the netlists to build the in-memory design database link_design -top wave_gen # Implement the design in Non-Project Mode opt_design place_design route_design # write out an implemented design checkpoint write_checkpoint -force wave_gen_post_route.dcp
All black boxes for that IP customization are replaced with the netlist from the synthesized DCP when the design is linked, and the design constraints are applied to each instance.