Step 1: Open the Project - 2021.1 English

Vivado Design Suite Tutorial: Designing with IP (UG939)
Document ID
UG939
Release Date
2021-07-19
Version
2021.1 English
  1. From the Getting Started page, select Open Project and browse to: <extract_dir>/lab_1/project_wave_gen_ip.
  2. On Windows, select Start > All Programs > Xilinx Design Tools > Vivado 2021.1 > Vivado 2021.1 to launch the Vivado® Design Suite.
  3. As an alternative, click the Vivado 2021.1 Desktop icon to start the Vivado IDE.

    The Vivado IDE Getting Started page, shown in the following figure, contains links to open or create projects and to view documentation.



  4. From the Open Project window, shown in the following figure, select project_wave_gen_ip.xpr, and click OK.

    The design loads and you see the Vivado IDE in the default layout view, with the Project Summary information as shown in the following figure.



    Because this is an RTL project, you can run behavioral simulation, elaborate the design, launch synthesis and implementation, and generate a bitstream for the device. The Vivado IDE also offers a one-button flow to generate a bitstream, which will automatically launch synthesis and implementation. For more information, see the Vivado Design Suite User Guide: Using the Vivado IDE (UG893).